The present invention relates to a semiconductor integrated circuit, and more particularly to an improved layout of a switching circuit in a semiconductor integrated circuit.
In recent years, high-density circuit integration has remarkably progressed as represented by dynamic MOS memories. In proportion to such high-density circuit integration, a number of circuits adapted to receive a switching signal generated by one switching circuit has been increased. For instance, in a 64-kilobit dynamic memory, 512 digit lines are simultaneously precharged in response to the same switching signal. More particularly, at least 512 precharging insulated gate field effect transistors (IGFET's) connected to the 512 digit lines must be controlled by the single switching signal. Therefore, a resistance of wirings connecting the respective IGFET's and the switching signal generator and total gate capacitances of the IGFET's become very large. This means that the time constant of the load of the single switching signal is very large and the switching speed is eventually lowered.
If the width of the wirings is broadened, the resistance of the wirings can be reduced, but a high density arrangement of circuit elements is remarkably prevented. Therefore, this measure is not practical.
It is a matter of course that such problem exists not only in a precharge circuit but also, for example, in the case where the same timing or switching signal is fed to a large number of IGFET's.